This invention relates to the field of integrated circuit (IC) design. Specifically, it discloses a clock system capable of using an external system clock for driving at least one voltage generator circuit of an embedded semiconductor memory unit. The clock system is designed to reduce power consumption while minimizing the amount of surface area required in implementing the memory unit, maximizing system performance and maintaining the integrity of the data stored within the embedded memory unit.
Semiconductor memory units embedded within an integrated circuit (IC) system are arranged in arrays of cells, where each cell stores one bit of information (1 or 0). Generally, in order to maintain the integrity of the data stored within an embedded semiconductor memory unit, such as an embedded dynamic random access memory unit (eDRAM), each cell of the memory unit requires periodic refreshing, since a small amount of charge stored in each cell of the memory unit tends to leak off. Additionally, the charge must be restored when a particular cell is read. Accordingly, circuitry is required to manage or control such semiconductor memory units.
This circuitry may be an IC memory unit controller chip or other logic ICs external to the memory unit. When the circuitry, especially the refresh circuitry, is incorporated within the memory unit, the memory unit is called pseudostatic or quasi-static, such as a quasi-static RAM memory unit. A memory unit that has most of the controller functions incorporated within is referred to as integrated, such as an integrated RAM memory unit. For a large memory system using several memory units, the redundancy of having the controller circuitry on every memory unit would not be economical.
The power supplies for normal and refresh operations generally include several voltage generators, including charge pump circuits, to provide different voltage and current supplies to cells and other circuits of the memory unit. For example, three typical charge pump circuits for the eDRAM are the substrate bias circuit or Vbb charge circuit, the negative word-line-low bias circuit or Vwl charge circuit, and the boost word-line-high voltage or Vpp charge circuit. A respective constant-speed ring oscillator provided in proximity or within the memory unit is generally used to run each of these charge circuits. A typical frequency range for the oscillator is from 5 MHZ to 50 MHZ depending on the voltage or current required to be produced by the particular charge circuit.
For example, for the Vbb charge circuit, the required capacity is low, and therefore, a 5 MHZ oscillator is sufficient. On the other hand, for the Vwl charge circuit, which is designed to sink large amount of current during an active mode, a 40 MHZ oscillator is required. However, during a standby or sleep mode, when there is no access to the word-lines, a lower capacity standby charge circuit supported by a lower-speed oscillator is needed for the Vwl charge circuit to save power. Therefore, two oscillator circuits with different capacities are needed for the Vwl charge circuit, i.e., one for each mode, thereby necessitating the use of additional surface area in implementing the memory unit.
Further, when the operating voltage, i.e, Vdd, of the memory unit starts to drop, e.g., when power output from a battery decreases, the charge produced by the charge circuits is affected. For example, if the peak current provided by the Vpp charge circuit is 4 mA when Vdd is 1.8V, when the Vdd drops from 1.8V to 1.5V and lower, the peak current provided by the Vpp charge circuit is much less than 4 mA. This results in performance degradation of the memory unit which could lead to data corruption or loss, since the cells of the memory unit would not be adequately restored or refreshed.
Additionally, prior art memory units are designed for the oscillator circuit(s) of the charge circuits to keep running, even when the memory unit is in a standby or sleep mode. This causes substrate noise due to the unnecessary current being injected into the substrate of the memory unit. Substrate noise could cause the circuitry within the memory unit to overheat and thereby, lead to data corruption or loss.
Accordingly, a need exists for a system for driving charge pump circuits of a memory unit, such as an eDRAM memory unit, which reduces power consumption, minimizes the surface area required in implementing the memory unit, maximizes system performance and maintains the integrity of the data stored within the memory unit.
The present invention is essentially a clock system for an embedded semiconductor memory unit. The clock system is capable of using an external system clock for driving at least one charge pump circuit of the semiconductor memory unit for restoring and refreshing a data array of the memory unit. The clock system is designed to reduce power consumption while minimizing the chip surface area required in implementing the memory unit, maximizing system performance and maintaining the integrity of the data.
In one embodiment, the clock system includes a plurality of control circuits each having a clock select circuit which has as an input the external system clock, an internal clock generator circuit for generating an internal system clock, and a multiplexer. The multiplexer has as inputs an output of the clock select circuit, i.e., the external system clock, and an output of the internal clock generator circuit, i.e., the internal system clock. The multiplexer outputs either the external system clock or the internal system clock to the at least one charge pump circuit according to at least one control signal transmitted by a central processing unit to the clock select circuit.
The control signal to the clock select circuit can, for example, be a sleep signal which causes a clock signal to the at least one charge pump circuit of the memory unit to be generated by the internal clock generator circuit. That is for the multiplexer to select the internal system clock for driving the at least one charge pump circuit. It is necessary to have both external and internal clock supplies, because during sleep mode, the external clock from the system may not be available. The control signal to the clock select circuit can also be an active mode signal which causes the clock signal to the at least one charge pump circuit of the memory unit to come from a system clock. That is for the multiplexer to select the external system clock for driving the at least one charge pump circuit. The control signal to the clock select circuit can also be a disable clock signal for disabling the clock select circuit. That is for the multiplexer to select the internal system clock for driving the at least one charge pump circuit.
In another embodiment, a clock system, in accordance with the principles of the invention, is designed to be incorporated within electronic devices powered by batteries. The clock system prevents performance degradation of the memory unit which can lead to data corruption or loss when power output from a battery decreases, i.e., when the supply voltage decreases. The clock system selects the appropriate clock frequency for driving a charge pump circuit of the memory unit according to the supply voltage. When the supply voltage drops, a higher clock frequency is selected by the clock system for driving the charge pump circuit of the memory unit and thus, maintain the charge capacity of the charge circuit and the integrity of the data stored within the memory unit.
In a further embodiment, a clock system, in accordance with the principles of the invention, adjusts or controls the magnitude of the charge pump capacity of a charge pump circuit by changing the clock frequency routed to the charge pump circuit. This embodiment allows the clock system to drive the charge pump circuit between a high-power mode and a low-power mode depending on the clock frequency.
In yet another embodiment of the present invention, a clock is provided from the eDRAM unit during sleep mode to the memory controller or core so that the refresh clock and other clocks will be available to perform a low-power sleep operation.